LAN83C185 Datasheet, PDF (42/61 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Table 5.50 Register 29 - Interrupt Source Flags (continued)
Datasheet
ADDRESS
NAME
29.6
INT6
29.5
INT5
29.4
INT4
29.3
INT3
29.2
INT2
29.1
INT1
29.0
Reserved
DESCRIPTION
1 = Auto-Negotiation complete
0 = not source of interrupt
1 = Remote Fault Detected
0 = not source of interrupt
1 = Link Down (link status negated)
0 = not source of interrupt
1 = Auto-Negotiation LP Acknowledge
0 = not source of interrupt
1 = Parallel Detection Fault
0 = not source of interrupt
1 = Auto-Negotiation Page Received
0 = not source of interrupt
MODE DEFAULT
RO/
0
LH
RO/
0
LH
RO/
0
LH
RO/
0
LH
RO/
0
LH
RO/
0
LH
RO/
0
LH
ADDRESS
NAME
30.15:8
30.7:0
Reserved
Mask Bits
Table 5.51 Register 30 - Interrupt Mask
DESCRIPTION
Write as 0; ignore on read.
1 = interrupt source is enabled
0 = interrupt source is masked
MODE DEFAULT
RO
0
RW
0
Table 5.52 Register 31 - PHY Special Control/Status
ADDRESS
NAME
31.15
Reserved
31.14
Reserved
31.13
Special
31.12
Autodone
31.11:10
31.9:7
Reserved
GPO[2:0]
31.6
Enable 4B5B
31.5
Reserved
DESCRIPTION
Do not write to this register. Ignore on read.
Must be set to 0
Auto-negotiation done indication:
0 = Auto-negotiation is not done or disabled (or not
active)
1 = Auto-negotiation is done
General Purpose Output connected to signals
GPO[2:0]
0 = Bypass encoder/decoder.
1 = enable 4B5B encoding/decoding.
MAC Interface must be configured in MII mode.
Write as 0, ignore on Read.
MODE DEFAULT
RW
0
RW
0
RO
0
RW
0
RW
0
RW
1
RW
0
Rev. 0.8 (11-16-04)
42
DATASHEET
SMSC LAN83C185