LAN83C185 Datasheet, PDF (24/61 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER

4.6.1
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
MII
The MII includes 16 interface signals:
■ transmit data - TXD[3:0]
■ transmit strobe - TX_EN
■ transmit clock - TX_CLK
■ transmit error - TX_ER/TXD4
■ receive data - RXD[3:0]
■ receive strobe - RX_DV
■ receive clock - RX_CLK
■ receive error - RX_ER/RXD4
■ collision indication - COL
■ carrier sense - CRS
In MII mode, on the transmit path, the PHY drives the transmit clock, TX_CLK, to the controller. The
controller synchronizes the transmit data to the rising edge of TX_CLK. The controller drives TX_EN
high to indicate valid transmit data. The controller drives TX_ER high when a transmit error is detected.
On the receive path, the PHY drives both the receive data, RXD[3:0], and the RX_CLK signal. The
controller clocks in the receive data on the rising edge of RX_CLK when the PHY drives RX_DV high.
The PHY drives RX_ER high when a receive error is detected.
4.7
Auto-negotiation
The purpose of the Auto-negotiation function is to automatically configure the PHY to the optimum link
parameters based on the capabilities of its link partner. Auto-negotiation is a mechanism for
exchanging configuration information between two link-partners and automatically selecting the highest
performance mode of operation supported by both sides. Auto-negotiation is fully defined in clause 28
of the IEEE 802.3 specification.
Once auto-negotiation has completed, information about the resolved link can be passed back to the
controller via the Serial Management Interface (SMI). The results of the negotiation process are
reflected in the Speed Indication bits in register 31, as well as the Link Partner Ability Register
(Register 5).
The auto-negotiation protocol is a purely physical layer activity and proceeds independently of the MAC
controller.
The advertised capabilities of the PHY are stored in register 4 of the SMI registers. The default
advertised by the PHY is determined by user-defined on-chip signal options.
The following blocks are activated during an Auto-negotiation session:
■ Auto-negotiation (digital)
■ 100M ADC (analog)
■ 100M PLL (analog)
■ 100M equalizer/BLW/clock recovery (DSP)
■ 10M SQUELCH (analog)
■ 10M PLL (analog)
■ 10M Transmitter (analog)
When enabled, auto-negotiation is started by the occurrence of one of the following events:
■ Hardware reset
■ Software reset
Rev. 0.8 (11-16-04)
24
DATASHEET
SMSC LAN83C185