SI53360 Datasheet, PDF (9/15 Pages) Silicon Laboratories – 1:8 LOW JITTER CMOS CLOCK BUFFER WITH 2:1 INPUT MUX

Si53360
Table 9. Si53360 Pin Description* (Continued)
Pin #
Name
Type*
Description
15
V_DD
16
CLK_SEL
P Core voltage supply.
Bypass with 1.0 F capacitor and place as close to the V_DD pin as possible.
I Mux input select pin (LVCMOS).
When CLK_SEL is high, CLK1 is selected.
When CLK_SEL is low, CLK0 is selected.
CLK_SEL features an internal pull-up resistor.
*Note: Pin types are: I = input, O = output, P = power, GND = ground.
Rev. 1.1
9