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SI53360 Datasheet, PDF (4/15 Pages) Silicon Laboratories – 1:8 LOW JITTER CMOS CLOCK BUFFER WITH 2:1 INPUT MUX | |||
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Si53360
Table 5. AC Characteristics
(VDD = 1.8 V ï±ï 5%, 2.5 V ï± 5%, or 3.3 V ï±ï 10%,TA = â40 to 85 ï°C)
Parameter
Frequency
Duty Cycle
Note: 50% input duty
cycle.
Minimum Input Clock
Slew Rate
Output Rise/Fall Time
Symbol
F
DC
SR
TR/TF
Test Condition
LVCMOS
200 MHz, 50 ïï toï VDD/2ï¬ï 20/80%ï
TR/TF<10% of period
Required to meet prop delay and
additive jitter specifications
(20â80%)
200 MHz, 50 ïï¬ï 20/80%,
2 pF load, 12 mA drive strength
Min
dc
40
0.75
â
Minimum Input Pulse
TW
2
Width
Additive Jitter
J
3.3 V, 200 MHz,
â
(12 kHz - 20 MHz)
Vin = 1.7 VPP @ 1 V/ns
3.3 V, 156.25 MHz,
â
Vin = 2.18 VPP @ 1 V/ns
2.5 V, 200 MHz,
â
Vin = 1.7 VPP @ 1 V/ns
2.5 V, 156.25 MHz,
â
Vin = 2.18 VPP @ 1 V/ns
Propagation Delay
TPLH,
Low-to-high, high-to-low
1.5
TPHL
Single-ended
CL = 2 pF
Output Enable Time
TEN
F = 1 MHz
â
F = 100 MHz
â
Output Disable Time
TDIS
F = 1 MHz
â
F = 100 MHz
â
Part to Part Skew
TSKPP
CL = 2 pF
0
Output to Output
TSK
CL = 2 pF
â
Skew
Typ
Max
Unit
â
200
MHz
50
60
%
â
â
V/ns
â
850
ps
â
â
ns
130
180
fs-rms
125
220
fs-rms
115
250
fs-rms
125
240
fs-rms
3.0
4.5
ns
10
â
ns
10
â
ns
20
â
ns
20
â
ns
300
ps
20
80
ps
4
Rev. 1.1
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