SI53360 Datasheet, PDF (6/15 Pages) Silicon Laboratories – 1:8 LOW JITTER CMOS CLOCK BUFFER WITH 2:1 INPUT MUX

Si53360
2. Functional Description
The Si53360 is a low jitter, low skew 1:8 CMOS buffer with an integrated 2:1 input mux. A clock select pin is used
to select the active input clock. An asynchronous output enable pin is available for additional control.
2.1. Input Termination
Figure 1 shows the recommended input clock termination.
V_{DDO= 3.3 V, 2.5 V, 1.8 V}
CMOS
Rs
Driver
50
V_DD
CLKx
Si533xx
Note: V_DDO and V_DD must be at the same voltage level.
Figure 1. LVCMOS DC-Coupled Input Termination
2.2. Input Mux
The Si53360 provides two clock inputs for applications that need to select between one of two clock sources. The
CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the
input mux and output enable pin settings. If one of the input clocks is unused, leave floating.
Table 8. Input Mux and Output Enable Logic
CLK_SEL CLK0
CLK1
OE¹
Q²
L
L
X
H
L
L
H
X
H
H
H
X
L
H
L
H
X
H
H
H
X
X
X
L
Tri-state
Notes:
1. Output enable active high.
2. On the next negative transition of CLK0 or CLK1.
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Rev. 1.1