SI53360 Datasheet, PDF (8/15 Pages) Silicon Laboratories – 1:8 LOW JITTER CMOS CLOCK BUFFER WITH 2:1 INPUT MUX

Si53360
3. Pin Description: 16-TSSOP
OE ¹
VDD ₂
Q0 3
Q1 4
Q2 5
Q3 6
GND 7
CLK0 8
16 _{CLK_SEL}
15 _VDD
14 _Q7
13 Q6
12 Q5
11 _Q4
10 _GND
9 _CLK1
Table 9. Si53360 Pin Description*
Pin #
1
Name
OE
2
V_DD
3
Q0
Type*
Description
I Output enable.
When OE= high, the clock outputs are enabled.
When OE= low, the clock outputs are tri-stated.
OE features an internal pull-up resistor, and may be left unconnected.
P Core voltage supply.
Bypass with 1.0 F capacitor and place as close to the V_DD pin as possible.
O Output clock 0.
4
Q1
5
Q2
O Output clock 1.
O Output clock 2.
6
Q3
O Output clock 3.
7
GND
GND Ground.
8
CLK0
I Input clock 0.
9
CLK1
I Input clock 1.
10
GND
GND Ground.
11
Q4
O Output clock 4.
12
Q5
13
Q6
O Output clock 5.
O Output clock 6.
14
Q7
O Output clock 7.
*Note: Pin types are: I = input, O = output, P = power, GND = ground.
8
Rev. 1.1