SI53360 Datasheet, PDF (12/15 Pages) Silicon Laboratories – 1:8 LOW JITTER CMOS CLOCK BUFFER WITH 2:1 INPUT MUX

Si53360
6. PCB Land Pattern
6.1. 16-TSSOP Package Land Pattern
Figure 5. Si53360 16-TSSOP Package Land Pattern
Table 11. PCB Land Pattern
Dimension
Feature
C1
Pad Column Spacing
(mm)
5.80
E
Pad Row Pitch
0.65
X1
Pad Width
0.45
Y1
Pad Length
1.40
Notes:
1. This Land Pattern Design is based on IPC-7351
specifications for Density Level B (Median Land
Protrusion).
2. All feature sizes shown are at Maximum Material
Condition (MMC) and a card fabrication tolerance of
0.05 mm is assumed.
12
Rev. 1.1