SI53106 Datasheet, PDF (9/34 Pages) Silicon Laboratories – SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53106
Table 6. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)¹
Parameter
Symbol
CLK 100 MHz, 133 MHz
Clock Stabilization Time
T_STAB
Long Term Accuracy
L_ACC
Absolute Host CLK Period (100MHz) T_ABS
Absolute Host CLK Period (133MHz) T_ABS
Edge Rate
Edge_rate
Min
—
—
9.94900
7.44925
1.0
Typ
Max
1.5
1.8
—
100
—
10.05100
—
7.55075
—
4.0
Rise Time Variation
∆ T_RISE
—
—
125
Fall Time Variation
∆ T_FALL
—
—
125
Rise/Fall Matching
T_{RISE_MAT}/
—
—
20
T_{FALL_MAT}
Voltage High (typ 0.7 V)
V_HIGH
660
—
850
Voltage Low (typ 0.7 V)
V_LOW
–150
—
150
Maximum Voltage
V_MAX
—
—
1150
Absolute Crossing Point Voltages
Vox_ABS
250
—
550
Unit
ms
ppm
ns
ns
V/ns
ps
ps
%
mV
mV
mV
mV
Total Variation of V_CROSS Over All
Total ∆
—
Edges
Vox
Duty Cycle
DC
45
Maximum Voltage (Overshoot)
Maximum Voltage (Undershoot)
V_ovs
—
V_uds
—
—
140
mV
—
55
%
—
V_High + 0.3
V
—
V_Low – 0.3
V
Notes
2
3_,4_,5
3_,4_,6
3_,4_,6
3_,4_,7
3_,8_,9
3_,8_,9
3_,8_,10_,11
3_,8_,12
3_,8_,13
8
3_,8_,14_,15_,
16
3_,8_,18
3_,4
3_,8_,19
3_,8_,20
Rev. 1.2
9