SI53106 Datasheet, PDF (11/34 Pages) Silicon Laboratories – SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53106
Table 7. Clock Periods Differential Clock Outputs with SSC Disabled
SSC ON
Measurement Window
Unit
Center
Freq, MHz ^{1 Clock}
1 µs
0.1 s
0.1 s
0.1 s
1 µs
1 Clock
–C–C
Jitter
AbsPer
Min
–SSC
Short
Term AVG
Min
–ppm
Long
Term AVG
Min
0 ppm
Period
Nominal
+ppm
Long
Term AVG
Max
+SSC
Short
Term AVG
Max
+C–C
Jitter
AbsPer
Max
100.00 9.94900
9.99900 10.00000 10.00100
10.05100
ns
133.33 7.44925
7.49925 7.50000 7.50075
7.55075
ns
Table 8. Clock Periods Differential Clock Outputs with SSC Enabled
SSC ON
Measurement Window
Unit
Center
Freq, MHz ^{1 Clock}
1 µs
0.1 s
0.1 s
0.1 s
1 µs
1 Clock
–C–C
Jitter
AbsPer
Min
–SSC
Short
Term AVG
Min
–ppm
Long
Term AVG
Min
0 ppm
Period
Nominal
+ppm
Long
Term AVG
Max
+SSC
Short
Term AVG
Max
+C–C
Jitter
AbsPer
Max
99.75
9.94900 9.99900 10.02406 10.02506 10.02607 10.05126 10.10126
ns
133.33 7.44925 7.49925 7.51805 7.51880 7.51955 7.53845 7.58845
ns
Table 9. Absolute Maximum Ratings
Parameter
3.3 V Core Supply Voltage¹
3.3 V I/O Supply Voltage¹
3.3 V Input High Voltage^1,2
3.3 V Input Low Voltage¹
Storage Temperature¹
Input ESD protection³
Symbol
V_DD/V_{DD_A}
V_{DD_IO}
V_IH
V_IL
t_s
ESD
Min
—
—
—
−0.5
–65
2000
Max
4.6
4.6
4.6
—
150
—
Notes:
1. Consult manufacturer regarding extended operation in excess of normal dc operating parameters.
2. Maximum V_IH is not to exceed maximum V_DD.
3. Human body model.
Unit
V
V
V
V
°C
V
Rev. 1.2
11