SI53106 Datasheet, PDF (13/34 Pages) Silicon Laboratories – SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53106
2.4. SA_0, SA_1—Address Selection
SA_0 and SA_1 are tri-level hardware pins, which program the appropriate address for the Si53106. The two tri-
level input pins that can configure the device to nine different addresses.
Table 12. SMBUS Address Table
SA_1
L
L
L
M
M
M
H
H
H
SA_0
L
M
H
L
M
H
L
M
H
SMBUS Address
D8
DA
DE
C2
C4
C6
CA
CC
CE
2.5. PWRGD/PWRDN
PWRGD is asserted high and deasserted low. Deassertion of PWRGD (pulling the signal low) is equivalent to
indicating a power-down condition. PWRGD (assertion) is used by the Si53106 to sample initial configurations,
such as frequency select condition and SA selections. After PWRGD has been asserted high for the first time, the
pin becomes a PWRDN (Power Down) pin that can be used to shut off all clocks cleanly and instruct the device to
invoke power-saving mode. PWRDN is a completely asynchronous active low input. When entering power-saving
mode, PWRDN should be asserted low prior to shutting off the input clock or power to ensure all clocks shut down
in a glitch free manner. When PWRDN is asserted low, all clocks will be disabled prior to turning off the VCO. When
PWRDN is deasserted high, all clocks will start and stop without any abnormal behavior and will meet all ac and dc
parameters.
Note: The assertion and deassertion of PWRDN is absolutely asynchronous.
Warning: Disabling of the CLK_IN input clock prior to assertion of PWRDN is an undefined mode and not recommended.
Operation in this mode may result in glitches, excessive frequency shifting, etc.
Table 13. PWRGD/PWRDN Functionality
PWRGD/
PWRDN
0
1
DIF
Low
Normal
DIF
Low
Normal
Rev. 1.2
13