SI53106 Datasheet, PDF (28/34 Pages) Silicon Laboratories – SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53106
Pin #
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Name
DIF_2
VDD
NC
DIF_3
DIF_3
OE_3
VDD_IO
DIF_4
DIF_4
OE_4
NC
VDD
DIF_5
DIF_5
OE_5
VDDA
GNDA
GND
Table 25. Si53106 40-Pin QFN Descriptions
Type
Description
O, DIF 0.7 V Differential clock output. Default is 1:1.
3.3 V 3.3 V power supply for output.
- Do not connect this pin to anything.
O, DIF 0.7 V Differential clock output. Default is 1:1.
O, DIF 0.7 V Differential clock output. Default is 1:1.
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
VDD Power supply for differential outputs.
O, DIF 0.7 V Differential clock output. Default is 1:1.
O, DIF 0.7 V Differential clock output. Default is 1:1.
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
- Do not connect this pin to anything.
3.3 V 3.3 V power supply for outputs.
O, DIF 0.7 V Differential clock output. Default is 1:1.
O, DIF 0.7 V Differential clock output. Default is 1:1.
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
3.3 V 3.3 V power supply for outputs.
GND Ground for outputs.
GND Connect epad to ground.
28
Rev. 1.2