SI53106 Datasheet, PDF (6/34 Pages) Silicon Laboratories – SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53106
Table 4. Clock Input Parameters
T_A = –40 to 85 °C; supply voltage V_DD = 3.3 V ±5%
Parameter
Symbol
Test Condition
Input Frequency
F_IN
Bypass Mode
PLL Mode, 100 MHz
PLL Mode, 133.33 MHz
Input High Voltage- CLK_IN
V_IHDIF
Differential inputs
single-ended measurement
Input Low Voltage- CLK_IN
V_ILDIF
Differential inputs
single-ended measurement
Input Common Mode
Voltage - CLK_IN
V_COM
Common Mode Voltage Input
Input Amplitude- CLK_IN
V_Swing
Peak to Peak
Input Slew Rate- CLK_IN IDD_VDDAPD Measured differentially
Input Leakage Current
I_IN
V_IN = V_DD, V_IN = GND
Input Duty Cycle
d_tin
Measured from differential
waveform
Input Jitter, Cycle-Cycle
J_DIFIN
Differential measurement
Input SS Modulation Fre-
quency
f_MODIN Triangle Wave Modulation
Min
Typ Max
33
—
150
90
100 110
120 133.33 147
600
800 1150
V_SS –300
0
300
—
300
1000
300
— 1450
0.4
—
8
-5
—
5
45
—
55
0
—
125
30
—
33
Unit
MHz
MHz
MHz
mV
mV
mV
V/ns
A
%
ps
kHz
6
Rev. 1.2