SI53106 Datasheet, PDF (30/34 Pages) Silicon Laboratories – SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53106
8. Package Outline
Figure 12 illustrates the package details for the Si53106. Table 26 lists the values for the dimensions shown in the
illustration.
Figure 12. 40-Pin Quad Flat No Lead (QFN) Package
Table 26. Package Diagram Dimensions
Dimension
Min
A
0.80
Nom
Max
0.85
0.90
A1
0.00
0.02
0.05
b
0.15
0.20
0.25
D
5.00 BSC.
D2
2.65
2.80
2.95
e
0.40 BSC.
E
5.00 BSC.
E2
2.65
2.80
2.95
L
0.30
0.40
0.50
aaa
0.10
bbb
0.07
ccc
0.1
ddd
0.05
eee
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220
30
Rev. 1.2