SI5023 Datasheet, PDF(9/28 Page) Silicon Laboratories – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER

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SI5023 Datasheet, PDF (9/28 Pages) Silicon Laboratories – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER

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Si5023

Table 4. AC Characteristics (PLL Characteristics)

(VDD = 3.3 V Â±5%, TA = â40 to 85 Â°C)

Parameter

Symbol

Test Condition

Min

Typ

Max Unit

Jitter Tolerance

(OC-48)*

JTOL(PP)

f = 600 Hz

f = 6000 Hz

f = 100 kHz

f = 1 MHz

0.3

Jitter Tolerance

(OC-12 Mode)*

JTOL(PP)

f = 30 Hz

f = 300 Hz

f = 25 kHz

f = 250 kHz

0.4

Jitter Tolerance

(OC-3 Mode)*

JTOL(PP)

f = 30 Hz

f = 300 Hz

f = 6.5 kHz

f = 65 kHz

0.4

Jitter Tolerance (Gigabit Ethernet) TJT(PP) IEEE 802.3z Clause 38.6.8 600

Receive Data Total Jitter

Tolerance

UIPP

Jitter Tolerance (Gigabit Ethernet) DJT(PP) IEEE 802.3z Clause 38.6.9 370

Receive Data Deterministic Jitter

Tolerance

RMS Jitter Generation*

JGEN(RMS) with no jitter on serial data â

3.0

5.0 mUI

Peak-to-Peak Jitter Generation*

JGEN(PP) with no jitter on serial data

mUI

Jitter Transfer Bandwidth*

JBW

OC-48 Mode

2.0 MHz

OC-12 Mode

500 kHz

Jitter Transfer Peaking*

Acquisition TimeâOC-48

(Reference clock applied)

OC-3 Mode

130 kHz

0.03

0.1

TAQ

After falling edge of

1.6

2.2

RESET/CAL

From the return of valid

100

500

Âµs

data

Acquisition TimeâOC-48

(Reference-less operation)

TAQ

After falling edge of

2.0

5.5

RESET/CAL

From the return of valid

1.5

2.5

5.5

data

Reference Clock Range

See Table 8 on page 13

â 155.52 â

77.76

19.44

MHz

Input Reference Clock Frequency

Tolerance

CTOL

â500

500 ppm

Frequency Difference at which

Â±650

ppm

Receive PLL goes out of Lock

(REFCLK compared to the divided

down VCO clock)

*Note: As defined in Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 223 â 1 data pattern.

Rev. 1.25

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