SI5023 Datasheet, PDF (7/28 Pages) Silicon Laboratories – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5023
Table 2. DC Characteristics
(V_DD = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol Test Condition Min Typ Max Unit
Supply Current¹
FEC (2.7 GHz)
OC-48
GbE
OC-12
OC-3
I_DD
—
173
184
mA
—
170
180
—
175
185
—
180
190
—
190
197
Power Dissipation
FEC (2.7 GHz)
OC-48
GbE
OC-12
OC-3
Common Mode Input Voltage (DIN)²
Common Mode Input Voltage (REFCLK)²
DIN Single-ended Input Voltage Swing²
DIN Differential Input Voltage Swing²
REFCLK Single-ended Input Voltage Swing²
REFCLK Differential Input Voltage Swing²
Input Impedance (DIN)
Differential Output Voltage Swing
(DOUT)
P_D
V_ICM
V_ICM
V_IS
V_ID
V_IS
V_ID
R_IN
V_OD
VDD =
3.3 V (±5%)
—
—
—
—
—
See Figure 17 1.30
See Figure 16 1.90
See Figure 1A 10
See Figure 1B 10
See Figure 1A 200
See Figure 1B 200
Line-to-Line
84
100 Ω Load 700
Line-to-Line
571
561
577
594
627
1.50
2.10
—
—
—
—
100
800
637
623
640
657
682
1.62
2.30
500
1000
750
1500
116
1000
mW
V
V
mV
mV
mV
mV
Ω
mV_PP
Differential Output Voltage Swing
(CLKOUT)
V_OD
100 Ω Load
700
800 1100 mV_PP
Line-to-Line
Output Common Mode Voltage
(DOUT,CLKOUT)
V_OCM
100 Ω Load
1.60 1.80
2.35
V
Line-to-Line
Output Impedance (DOUT,CLKOUT)
Input Voltage Low (LVTTL Inputs)
Input Voltage High (LVTTL Inputs)
Input Low Current (LVTTL Inputs)
Input High Current (LVTTL Inputs)
Input Impedance (LVTTL Inputs)
LOS_LVL, BER_LVL, SLICE_LVL Input
Impedance
R_OUT Single-ended
84
100
116
Ω
V_IL
—
—
.8
V
V_IH
2.0
—
—
V
I_IL
—
—
10
µA
I_IH
—
—
10
µA
R_IN
9
—
—
kΩ
R_IN
50
100
125
kΩ
Output Voltage Low (LVTTL Outputs)
Output Voltage High (LVTTL Outputs)
V_OL
I_O = 2 mA
—
—
0.4
V
V_OH
I_O = 2 mA
2.0
—
—
V
Notes:
1. No load on LVTTL outputs.
2. These inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input must be ac
coupled to ground.
Rev. 1.25
7