SI5023 Datasheet, PDF (27/28 Pages) Silicon Laboratories – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5023
DOCUMENT CHANGE LIST
Revision 1.21 to Revision 1.22
Updated "3.Typical Application Schematic" on page
11.
Updated Figure 11 on page 16.
Updated Table 9 on page 22.
Updated BERMON pin description.
Revision 1.22 to Revision 1.23
Updated Table 2 on page 7.
Added “Output Common Mode Voltage (Si5023)
(DOUT)” with updated values.
Added “Output Common Mode Voltage (Si5023)
(CLKOUT)” with updated values.
Updated Table 3 on page 8.
Added “Output Clock Duty Cycle OC-48/12/3”
Updated Table 9 on page 22.
Changed “clock input” to “DIN inputs” for Loss-of-Signal.
Updated Figure 22, “28-Lead Quad Flat No-Lead
(QFN),” on page 26.
Updated Table 10, “Package Diagram Dimensions,”
on page 26.
Changed dimension A.
Changed dimension E2.
Revision 1.24 to Revision 1.25
Updated Table 2 on page 7.
Added limits for V_ICM.
Updated V_OD.
Updated Table 3 on page 8.
Updated T_Cr-D.
Updated T_Cf-D.
Revised SLICE specification.
Updated Table 4 on page 9.
T_AQ min/max values updated.
Updated "4.8.Loss-of-Signal (LOS)" on page 13.
Added note describing valid signal.
Revised Figure 6, “LOS_LVL Mapping (PRBS23 Data),”
on page 14, showing internal noise limits.
Updated "4.9.Bit Error Rate (BER) Detection" on
page 14.
Revised Figure 8.
Added Figures 9 and 10.
Updated "4.10.Data Slicing Level" on page 14.
Added Figures 12 and 13.
Revised text.
Updated pin description for RATESEL.
Revision 1.23 to Revision 1.24
Removed all references to Si5022.
Updated Table 2 on page 7.
I_dd
P_d
R_IN
+V_ICM
+V_OD
+V_OCM
Updated Tables 3 and 4 on page 8.
Clarified f_CLK for the different settings of RATESEL
Revised duty cycle, t_CR-D, C_TOL
Revised slicing level accuracy
Updated Table 8 on page 13.
Removed OC3 support for 15/14 FEC
Updated "4.17.Voltage Regulator" on page 19.
Due to removal of Si5022 references
Updated "6.Ordering Guide" on page 25.
Added “X” to part number.
Rev. 1.25
27