SI5023 Datasheet, PDF (22/28 Pages) Silicon Laboratories – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5023
5. Pin Descriptions: Si5023
Pin #
1,2
3
4
RATESEL0
RATESEL1
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK-
LOL
28 27 26 25 24 23 22
1
21 VDD
2
20 REXT
3
19 RESET/CAL
4
GND
18 VDD
Pad
5
17 DOUT+
6
16 DOUT-
7
15 GND
8 9 10 11 12 13 14
Pin Name
RATESEL0,
RATESEL1
LOS_LVL
SLICE_LVL
Top View
Figure 21. Si5023 Pin Configuration
Table 9. Si5023 Pin Descriptions
I/O Signal Level
Description
I
LVTTL Data Rate Select.
These pins configure the onboard PLL for clock and
data recovery at one of four user selectable data
rates. See Table 7 for configuration settings.
Notes:
1. These inputs have weak internal pullups.
2. After any change in RATESEL, the device must be
reset.
I
LOS Level Control.
The LOS threshold is set by the input voltage level
applied to this pin. Figure 6 on page 14 shows the
input setting to output threshold mapping.
LOS is disabled when the voltage applied is less
than 1 V.
I
Slicing Level Control.
The slicing threshold level is set by applying a volt-
age to this pin as described in the Slicing Level sec-
tion of the data sheet. If this pin is tied to GND,
slicing level adjustment is disabled, and the slicing
level is set to the midpoint of the differential input
signal on DIN. Slicing level becomes active when
the voltage applied to the pin is greater than
500 mV.
22
Rev. 1.25