SI5023 Datasheet, PDF (24/28 Pages) Silicon Laboratories – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5023
Pin #
19
20
22
23
24
26
27
28
GND Pad
Table 9. Si5023 Pin Descriptions (Continued)
Pin Name
RESET/CAL
REXT
CLKOUT–
CLKOUT+
CLKDSBL
BER_LVL
BER_ALM
BERMON
GND
I/O Signal Level
Description
I
LVTTL Reset/Calibrate.
Driving this input high for at least 1 µs will reset
internal device circuitry. A high to low transition on
this pin will force a DSPLL calibration. For normal
operation, drive this pin low.
Note: This input has a weak internal pulldown.
External Bias Resistor.
This resistor is used to establish internal bias cur-
rents within the device. This pin must be connected
through a 10 kΩ (1%) resistor to GND.
O
CML
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN except when LTR is asserted or the
LOL state has been entered.
I
LVTTL Clock Disable.
When this input is high, the CLKOUT output drivers
are disabled. For normal operation, this pin should
be low.
Note: This input has a weak internal pulldown.
I
Bit Error Rate Level Control.
The BER threshold level is set by applying a volt-
age to this pin. The applied voltage is as described
in the BER_LVL section. When the BER exceeds
the programmed threshold, BER_ALM is driven low.
If this pin is tied to GND, BER_ALM is disabled.
O
LVTTL Bit Error Rate Alarm.
This pin will be driven low to indicate that the BER
threshold set by BER_LVL has been exceeded.
There is no hysteresis.
O
Bit Error Rate Monitor.
The voltage on this pin is proportional to the
detected bit error rate computed by the internal
BER processor. This voltage output has a range of
0 to 0.87 V. See Figure 8 on page 15.
The output is a current source, which requires a
5 kΩ (1%) resistor to GND to guarantee the operat-
ing range shown in Figure 8. This pin may be left
unconnected.
GND
Supply Ground.
Nominally 0.0 V. The 3 x 3 mm square GND pad
found on the bottom of the 28-lead micro leaded
package (see Figure 22) must be connected
directly to supply ground. Minimize the ground path
inductance for optimal performance.
24
Rev. 1.25