SI5023 Datasheet, PDF (8/28 Pages) Silicon Laboratories – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5023
Table 3. AC Characteristics (Clock and Data)
(V_DD = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Output Clock Rate
f_CLK
Output Clock Rise Time—OC-48
Output Clock Fall Time—OC-48
Output Clock Duty Cycle
OC-48/12/3
Output Data Rise Time—OC-48
Output Data Fall Time—OC-48
Clock-to-Data Delay
FEC (2.7 GHz)
OC-48
GbE
OC-12
OC-3
Clock to Data Delay
FEC (2.7 GHz)
OC-48
Input Return Loss
t_R
t_F
t_R
t_F
t_Cr-D
t_Cf-D
RATESEL[0:1] = 11
RATESEL[0:1] = 01
RATESEL[0:1] = 10
RATESEL[0:1] = 00
Figure 3 on page 6
Figure 3 on page 6
Figure 3 on page 6
Figure 3 on page 6
Figure 2 on page 5
Figure 2 on page 5
100 kHz–1.5 GHz
1.5 GHz–4.0 GHz
Slicing Level Offset
(relative to the internally set input
common mode voltage)
V_SLICE
SLICE_LVL = 750 mV to
2.25 V
Loss-of-Signal Range*
(peak-to-peak differential)
V_LOS LOS_LVL = 1.50 TO 2.50 V
Loss-of-Signal Response Time
t_LOS
Figure 5 on page 6
*Note: Adjustment voltage is calculated as follows: V_LOS = (LOS_LVL – 1.50)/25.
Min Typ
2.46
—
1.232 —
616
—
154
—
—
70
—
70
47
50
—
80
—
80
Max Unit
2.7 GHz
1.35 GHz
675 MHz
158 MHz
90
ps
90
ps
53 % of
UI
110
ps
110
ps
190
230
265
ps
190
230
265
440
490
560
800
860
940
4000 4100 4200
–70
–40
–10
ps
–60
–30
0
–15
—
–10
—
—
dB
—
dB
See Figures 12 and 13.
0
—
40
mV
8
20
25
µs
8
Rev. 1.25