SI5023 Datasheet, PDF (19/28 Pages) Silicon Laboratories – MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5023
4.17. Voltage Regulator
The Si5023 regulates 2.5 V internally down from the external 3.3 V supply. Consumption is typically 170 mA. The
Si5023 may accept control inputs as high as 3.6 V.
4.18. Differential Input Circuitry
The Si5023 provides differential inputs for both the high-speed data (DIN) and the reference clock (REFCLK)
inputs. Example terminations for these inputs are shown in Figures 16, 17, 18, and 19. In applications where direct
dc coupling is possible, the 0.1 µF capacitors may be omitted. (LOS operation is only guaranteed when ac
coupled.) The data input limiting amplifier requires an input signal with a differential peak-to-peak voltage as
specified in Table 2 on page 7 to ensure a BER of at least 10^–12. The REFCLK input differential peak-to-peak
voltage requirement is specified in Table 2.
Clock source
0.1 µF
0.1 µF
Zo = 50 Ω
100 Ω
Zo = 50 Ω
2.5 V (±5%)
2.5 kΩ
RFCLK +
10 kΩ
2.5 kΩ
RFCLK –
10 kΩ
GND
Figure 16. Input Termination for REFCLK (ac coupled)
TIA
0.1 µF
Zo = 50 Ω
0.1 µF
Zo = 50 Ω
DIN +,
50 Ω
DIN –,
50 Ω
2.5 V (±5%)
5 kΩ
7.5 kΩ
GND
Figure 17. Input Termination for DIN (ac coupled)
Rev. 1.25
19