SI5351-B Datasheet, PDF (8/41 Pages) Silicon Laboratories – Supports static phase offset

Si5351A/B/C-B
Table 7. Crystal Requirements^1,2
Parameter
Symbol
Min
Typ
Max
Unit
Crystal Frequency
f_XTAL
25
—
27
MHz
Load Capacitance
C_L
6
—
12
pF
Equivalent Series Resistance
r_ESR
—
—
150

Crystal Max Drive Level
d_L
100
—
—
µW
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF
capacitors on XA and XB).
2. Refer to “AN551: Crystal Selection Guide” for more details.
Table 8. I²C Specifications (SCL,SDA)¹
Parameter Symbol Test Condition
Standard Mode
100 kbps
Fast Mode
Unit
400 kbps
Min
Max
Min
Max
LOW Level
Input Voltage
HIGH Level
Input Voltage
Hysteresis of
Schmitt Trigger
Inputs
V_ILI2C
V_IHI2C
V_HYS
–0.5
0.3 x V_DDI2
C
–0.5
0.3 x V_DDI2C2 V
0.7 x V_DDI2
3.6
0.7 x V_DDI2C2
3.6
V
C
—
—
0.1
—
V
LOW Level
Output Voltage
(open drain or
open collector)
V_OLI2C2 V_DDI2C2 = 2.5/3.3 V
0
0.4
0
at 3 mA Sink
Current
0.4
V
Input Current
I_II2C
–10
10
–10
Capacitance for
Each I/O Pin
C_II2C
V_IN = –0.1 to V_DDI2C
—
4
—
I²C Bus
Timeout
T_TO
Timeout Enabled
25
35
25
10
µA
4
pF
35
ms
Notes:
1. Refer to NXP’s UM10204 I²C-bus specification and user manual, revision 03, for further details, go to:
www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.
2. Only I²C pullup voltages (VDDI2C) of 2.25 to 3.63 V are supported.
8
Rev. 1.0