SI5351-B Datasheet, PDF (7/41 Pages) Silicon Laboratories – Supports static phase offset

Si5351A/B/C-B
Table 6. Output Clock Characteristics
(V_DD = 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Frequency Range¹
Load Capacitance
Duty Cycle
Rise/Fall Time
Output High Voltage
Output Low Voltage
Period Jitter^2,3
Symbol
Test Condition
Min
Typ
F_CLK
C_L
DC
t_r
t_f
V_OH
V_OL
J_PER
0.0025
—
—
—
F_CLK < 160 MHz, Measured
at V_DD/2
45
50
F_CLK > 160 MHz, Measured
at V_DD/2
40
50
20%–80%, C_L = 5 pF,
—
1
Default high drive strength
—
1
C_L = 5 pF
V_DD – 0.6 —
—
—
20-QFN, 4 outputs running,
1 per VDDO
—
40
10-MSOP or 20-QFN,
all outputs running
—
70
Max
Unit
200
MHz
15
pF
55
%
60
%
1.5
ns
1.5
ns
—
V
0.6
V
95
ps, pk-
pk
155
ps, pk-
pk
Cycle-to-Cycle Jitter^2,3
20-QFN, 4 outputs running,
1 per VDDO
—
J_CC
10-MSOP or 20-QFN,
all outputs running
—
50
90
ps, pk
70
150 ps, pk
Period Jitter VCXO^2,3
20-QFN, 4 outputs running,
1 per VDDO
—
J_{PER_VCXO}
10-MSOP or 20-QFN,
all outputs running
—
50
95
ps, pk-
pk
70
155
ps, pk-
pk
Cycle-to-Cycle Jitter
VCXO^2,3
20-QFN, 4 outputs running,
1 per VDDO
—
J_{CC_VCXO}
10-MSOP or 20-QFN,
all outputs running
—
50
90
ps, pk
70
150 ps, pk
Notes:
1. Only two unique frequencies above 112.5 MHz can be simultaneously output.
2. Measured over 10K cycles. Jitter is only specified at the default high drive strength (50  output impedance).
3. Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world”
frequency plan; actual performance may be substantially better. Three-output 10 MSOP package measured with clock
outputs of 74.25, 24.576, and 48 MHz. Eight-output 20 QFN package measured with clock outputs of 33.333, 74.25,
27, 24.576, 22.5792, 28.322, 125, and 48 MHz.
Rev. 1.0
7