SI5351-B Datasheet, PDF (6/41 Pages) Silicon Laboratories – Supports static phase offset

Si5351A/B/C-B
Table 4. AC Characteristics
(V_DD = 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Power-up Time
Power-up Time, PLL Bypass
Mode
Output Enable Time
Output Frequency Transition
Time
T_RDY
T_BYP
T_OE
T_FREQ
From V_DD = V_DDmin to valid
output clock, C_L = 5 pF,
f_CLKn > 1 MHz
From V_DD = V_DDmin to valid
output clock, C_L = 5 pF,
f_CLKn > 1 MHz
From OEB pulled low to valid
clock output, C_L = 5 pF,
f_CLKn > 1 MHz
f_CLKn > 1 MHz
Output Phase Offset
Spread Spectrum Frequency
Deviation
P_STEP
SS_DEV
Down spread. Selectable in 0.1%
steps.
Center spread. Selectable in
0.1% steps.
Spread Spectrum Modulation
Rate
SS_MOD
VCXO Specifications (Si5351B only)
VCXO Control Voltage Range
Vc
VCXO Gain (configurable)
Kv
Vc = 10–90% of V_DD, V_DD = 3.3 V
VCXO Control Voltage Linearity KVL
Vc = 10–90% of V_DD
VCXO Pull Range
(configurable)
PR
V_DD = 3.3 V*
VCXO Modulation Bandwidth
*Note: Contact Silicon Labs for 2.5 V VCXO operation.
Min
—
—
—
—
—
–0.1
±0.1
30
0
18
–5
±30
—
Typ
2
0.5
—
—
333
—
—
31.5
V_DD/2
—
—
0
10
Max
10
1
10
10
—
–2.5
±1.5
33
V_DD
150
+5
±240
—
Unit
ms
ms
µs
µs
ps/step
%
%
kHz
V
ppm/V
%
ppm
kHz
Table 5. Input Clock Characteristics
(V_DD = 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Crystal Frequency
CLKIN Input Low Voltage
CLKIN Input High Voltage
CLKIN Frequency Range
f_XTAL
V_IL
V_IH
f_CLKIN
25
—
27
MHz
–0.1
—
0.3 x V_DD
V
0.7 x V_DD
—
3.60
V
10
—
100
MHz
6
Rev. 1.0