SI5351-B Datasheet, PDF (26/41 Pages) Silicon Laboratories – Supports static phase offset

Si5351A/B/C-B
9.2. Si5351B 20-Pin QFN
XA 1
XB 2
VC 3
SCL 4
SDA 5
GND
PAD
15 ^CLK7
14 ^VDDOD
13 ^CLK0
12 ^CLK1
11 ^VDDOA
Figure 20. Si5351B 20-QFN Top View*
Table 12. Si5351B Pin Descriptions
Pin Name
Pin
Number
Pin Type¹
Function
XA
1
I
Input pin for external crystal
XB
2
I
Input pin for external crystal
CLK0
13
O
Output clock 0
CLK1
12
O
Output clock 1
CLK2
9
O
Output clock 2
CLK3
8
O
Output clock 3
CLK4
19
O
Output clock 4
CLK5
17
O
Output clock 5
CLK6
16
O
Output clock 6
CLK7
15
O
Output clock 7
VC
3
SCL
4
SDA
5
I
VCXO control voltage input
I
I²C bus serial clock input. Pull-up to VDD core with 1 k
I/O I²C bus serial data input. Pull-up to VDD core with 1 k
SSEN
6
I
Spread spectrum enable. High = enabled, Low = disabled.
OEB
7
I
Output driver enable. Low = enabled, High = disabled.
VDD
20
P
Core voltage supply pin
VDDOA
11
P
Output voltage supply pin for CLK0 and CLK1. See 6.2
VDDOB
10
P
Output voltage supply pin for CLK2 and CLK3. See 6.2
VDDOC
18
P
Output voltage supply pin for CLK4 and CLK5. See 6.2
VDDOD
14
P
Output voltage supply pin for CLK6 and CLK7. See 6.2
GND Center Pad
P
Ground
1. I = Input, O = Output, P = Power
2. Input pins are not internally pulled up.
26
Rev. 1.0