SI5351-B Datasheet, PDF (14/41 Pages) Silicon Laboratories – Supports static phase offset

Si5351A/B/C-B
3.2. Synthesis Stages
The Si5351 uses two stages of synthesis to generate its final output clocks. The first stage uses PLLs to multiply
the lower frequency input references to a high-frequency intermediate clock. The second stage uses high-
resolution MultiSynth fractional dividers to generate the required output frequencies. Only two unique frequencies
above 112.5 MHz can be simultaneously output. For example, 125 MHz (CLK0), 130 MHz (CLK1), and 150 MHz
(CLKx) is not allowed. Note that multiple copies of frequencies above 112.5 MHz can be provided, for example,
125 MHz could be provided on four outputs (CLKS0-3) simultaneously with 130 MHz on four different outputs
(CLKS4-7).
A crosspoint switch at the input of the first stage allows each of the PLLs to lock to the CLKIN or the XTAL input.
This allows each of the PLLs to lock to a different source for generating independent free-running and synchronous
clocks. Alternatively, both PLLs could lock to the same source. The crosspoint switch at the input of the second
stage allows any of the MultiSynth dividers to connect to PLLA or PLLB. This flexible synthesis architecture allows
any of the outputs to generate synchronous or non-synchronous clocks, with spread spectrum or without spread
spectrum, and with the flexibility of generating non-integer related clock frequencies at each output.
All VCXO outputs are generated by PLLB only. The Multisynth high-resolution dividers synthesizes the VCXO
output’s center frequency up to 112.5 MHz. The center frequency is then controlled (or pulled) by the VC input. An
interesting feature of the Si5351 is that the VCXO output can be routed to more than one MultiSynth divider. This
creates a VCXO with multiple output frequencies controlled from one VC input as shown in Figure 5.
Frequencies down to 2.5 kHz can be generated by applying the R divider at the output of the Multisynth (see
Figure 5 below).
Fixed Frequency
XA
XB _{Crystal (non-pullable)}
Control ^VC
Voltage
OSC
VCXO
Multi
Synth
R0
0
Multi
Synth
R1
1
Multi
Synth
R2
2
CLK0
CLK1
CLK2
The clock frequency
generated from CLK0 is
controlled by the VC input
Additional MultiSynths
can be “linked” to the
VCXO to generate
additional clock
frequencies
Figure 5. Using the Si5351 as a Multi-Output VCXO
14
Rev. 1.0