SI5351-B Datasheet, PDF (21/41 Pages) Silicon Laboratories – Supports static phase offset

Si5351A/B/C-B
5.5. Replacing Crystals, Crystal Oscillators, and PLLs
The Si5351C generates synchronous clocks for applications that require a fully integrated PLL instead of a VCXO.
Because of its dual PLL architecture, the Si5351C is capable of generating both synchronous and free-running
clocks. An example is shown in Figure 15.
XA
25 MHz
OSC
PLL
XB
CLKIN
54 MHz
PLL
Si5351C
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Free-running
Clocks
CLK0
125 MHz
CLK1
48 MHz
CLK2
28.322 MHz
CLK3
74.25 MHz
CLK4 _{74.25/1.001 MHz}
CLK5
24.576 MHz
Ethernet
PHY
USB
Controller
HDMI
Port
Video/Audio
Processor
Synchronous
Clocks
Figure 15. Using the Si5351C to Replace Crystals, Crystal Oscillators, and PLLs
5.6. Applying a Reference Clock at XTAL Input
The Si5351 can be driven with a clock signal through the XA input pin. This is especially useful when in need of
generating clock outputs in two synchronization domains. With the Si5351C, one reference clock can be provided
at the CLKIN pin and at XA.
V_IN = 1 V_PP
25/27 MHz
XA
0.1 µF
XB
OSC
PLLA
PLLB
Note: Float the XB input while driving
the XA input with a clock
Multi
Synth
0
Multi
Synth
1
Multi
Synth
N
Figure 16. Si5351 Driven by a Clock Signal
Rev. 1.0
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