SI5351-B Datasheet, PDF (17/41 Pages) Silicon Laboratories – Supports static phase offset

Si5351A/B/C-B
Data is transferred MSB first in 8-bit words as specified by the I²C specification. A write command consists of a 7-
bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 9. A write
burst operation is also shown where every additional data word is written using to an auto-incremented address.
Write Operation – Single Byte
S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A P
Write Operation - Burst (Auto Address Increment)
S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A Data [7:0] A P
Reg Addr +1
From slave to master
From master to slave
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
Figure 9. I²C Write Operation
A read operation is performed in two stages. A data write is used to set the register address, then a data read is
performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
Figure 10.
Read Operation – Single Byte
S Slv Addr [6:0] 0 A Reg Addr [7:0] A P
S Slv Addr [6:0] 1 A Data [7:0] N P
Read Operation - Burst (Auto Address Increment)
S Slv Addr [6:0] 0 A Reg Addr [7:0] A P
S Slv Addr [6:0] 1 A Data [7:0] A Data [7:0] N P
Reg Addr +1
From slave to master
1 – Read
0 – Write
From master to slave
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
Figure 10. I²C Read Operation
AC and DC electrical specifications for the SCL and SDA pins are shown in Table 8. The timing specifications and
timing diagram for the I²C bus is compatible with the I²C-Bus Standard. SDA timeout is supported for compatibility
with SMBus interfaces.
Rev. 1.0
17