SI5351-B Datasheet, PDF (13/41 Pages) Silicon Laboratories – Supports static phase offset

Si5351A/B/C-B
3.1. Input Stage
3.1.1. Crystal Inputs (XA, XB)
The Si5351 uses a fixed-frequency standard AT-cut crystal as a reference to the internal oscillator. The output of
the oscillator can be used to provide a free-running reference to one or both of the PLLs for generating
asynchronous clocks. The output frequency of the oscillator will operate at the crystal frequency, either 25 MHz or
27 MHz. The crystal is also used as a reference to the VCXO to help maintain its frequency accuracy.
Internal load capacitors are provided to eliminate the need for external components when connecting a crystal to
the Si5351. The total internal XTAL load capacitance (C_L) can be selected to be 0, 6, 8, or 10 pF. Crystals with
alternate load capacitance requirements are supported using additional external load capacitance  2 pF (e.g., by
using  4 pF capacitors on XA and XB) as shown in Figure 4. Refer to application note AN551 for crystal
recommendations.
XA
XB
Optional additional
external load
capacitance
(< 2 pF)
Optional internal
load capacitance
0, 6, 8,10 pF
Figure 4. External XTAL with Optional Load Capacitors
3.1.2. External Clock Input (CLKIN)
The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs.
CLKIN can accept any frequency from 10 to 100 MHz. A divider at the input stage limits the PLL input frequency to
30 MHz.
3.1.3. Voltage Control Input (VC)
The VCXO architecture of the Si5351B eliminates the need for an external pullable crystal. Only a standard, low-
cost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.
The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the
VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90% of VDD), and
reliable startup and operation. Refer to Table 4 on page 6 for VCXO specification details.
A unique feature of the Si5351B is its ability to generate multiple output frequencies controlled by the same control
voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same
reference. An example is illustrated in Figure 5 on page 14.
Rev. 1.0
13