SI5334 Datasheet, PDF (8/37 Pages) Silicon Laboratories – PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5334
Table 4. Input and Output Clock Characteristics (Continued)
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
CMOS Output
Resistance
SSTL Output
Resistance
HSTL Output
Resistance
CMOS Output Volt-
age⁶
See Note ⁶
—
50
—

—
50
—

—
50
—

V_OH
4 mA load
VDDO – 0.3
—
V
V_OL
4 mA load
—
0.3
V
V_OH
0.45xVDDO+0.41 —
SSTL-3 VDDOx = 2.97
—
V
V_OL
to 3.63 V
—
—
0.45xVDDO–
0.41
V
V_OH
0.5xVDDO+0.41 —
SSTL-2 VDDOx = 2.25
SSTL Output Voltage
V_OL
to 2.75 V
—
—
—
V
0.5xVDDO–
0.41
V
V_OH
0.5xVDDO+0.34
SSTL-18 VDDOx = 1.71
—
V_OL
to 1.98 V
—
—
V
0.5xVDDO–
0.34
V
V_OH
HSTL Output Voltage
V_OL
Duty Cycle
DC
VDDO = 1.4 to 1.6 V
0.5xVDDO+0.3
—
45
—
—
V
— 0.5xVDDO –0.3 V
—
55
%
Notes:
1. Use an external 100  resistor to provide load termination for a differential clock.
See "2.2. Crystal/Clock Input" on page 15.
2. For best jitter performance, keep the input slew rate on IN1/2, IN5/6 faster than 0.3 V/ns.
3. For best jitter performance, keep the input single ended slew rate on pins 3 or 4 faster than 1 V/ns.
4. Only two unique frequencies above Fvco/8 can be simultaneously output, Fvco/4 and Fvco/6.
5. CML output format requires ac-coupling of the differential outputs to a differential 100  load at the receiver.
6. Includes effect of internal series 22  resistor.
8
Rev. 1.2