SI5334 Datasheet, PDF (5/37 Pages) Silicon Laboratories – PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5334
Table 3. Performance Characteristics
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
PLL Acquisition Time
t_ACQ
PLL Tracking Range
f_TRACK
PLL Loop Bandwidth
MultiSynth Frequency
Synthesis Resolution
f_BW
f_RES
Output frequency < Fvco/8
CLKIN Loss of Signal Assert
t_LOS
Time
CLKIN Loss of Signal Deassert t_{LOS_b}
Time
PLL Loss of Lock Detect Time
t_LOL
Min Typ Max
—
—
25
5000 20,000 —
—
1.6
—
0
0
1
—
2.6
5
0.01 0.2
1
—
5
10
POR to Output Clock Valid
t_RDY
—
—
2
Input-to-Output Propagation
Delay
Output-Output Skew
t_PROP
t_DSKEW
Buffer Mode
(PLL Bypass)
Rn divider = 1¹
—
2.5
4
—
—
100
Programmable Initial
Phase Offset
P_OFFSET
–45
—
+45
Phase Increment/Decrement
Accuracy
P_STEP
—
—
20
Phase Increment/Decrement
Range
Frequency range for phase
increment/decrement
P_RANGE
f_PRANGE
–45
—
+45
—
—
350²
Phase Increment/Decrement
Update Rate
Frequency Increment/
Decrement Step Size
Frequency Increment/
Decrement Range
Frequency Increment/
Decrement Update Rate
P_UPDATE
f_STEP
f_RANGE
f_UPDATE
Pin control
R divider not used³
R divider not used³
Pin control^2,3
—
— 1500
1
—
See
Note ³
—
—
350²
—
— 1500
Notes:
1. Outputs at integer-related frequencies and using the same driver format.
2. Keep MultiSynth output frequency between 5 MHz to Fvco/8.
3. Only MultiSynth0 can have frequency inc/dec but MultiSynth0 can be routed to any output.
4. Spread spectrum is only available on clock outputs that are at 100 MHz and have the Rn divider set to 1.
Unit
ms
ppm
MHz
ppb
µs
µs
ms
ms
ns
ps
ns
ps
ns
MHz
kHz
ppm
MHz
kHz
Rev. 1.2
5