SI5334 Datasheet, PDF (15/37 Pages) Silicon Laboratories – PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5334
The Si5334 is pin-controlled. No I²C interface is
provided. The LOLLOS output pin indicates the lock
condition of the PLL. An output enable input pin is
available on the Si5334A/B/C which affects all the
programmed clock outputs. All device specifications are
guaranteed across these three core supply voltages.
Packaged in a ROHS-6, Pb-free 4x4 mm QFN package,
the device supports the industrial temperature range of
–40 to +85 °C.
After core power is applied, the Si5334 downloads the
factory-programmed NVM into RAM and begins
operation.
2.2. Crystal/Clock Input
The device can be driven from either a low frequency
fundamental mode crystal (8–30 MHz) or an external
reference clock (5–710 MHz). The crystal is connected
across pins IN1 and IN2.
The PCB traces between the crystal and the device
must be kept very short to minimize stray capacitance.
To ensure maximum compatibility with crystals from
multiple vendors, the internal crystal oscillator provides
adaptive crystal drive strength based upon the crystal
frequency.
The crystal load capacitors are placed on-chip to reduce
external component count. If a crystal with a load
capacitance outside the range specified in Tables 2, 3,
and 12 is supplied to the device, it will result in a slight
ppm error in the device clock output frequencies. This
error can be compensated for by a small change in the
input to output multiplication ratio.
If a reference clock is used, the device accepts a single-
ended input reference on IN3 or a differential LVPECL,
LVDS, or HCSL source on IN1 and IN2. The input at IN3
can accept an input frequency up to 200 MHz. The
signal applied at IN3 should be dc-coupled because
internally this signal is ac-coupled to the receive input. A
single-ended reference clock up to 350 MHz can be ac-
coupled to IN1. A differential reference clock, such as
LVPECL, LVDS or HCSL, is input on IN1,2 for
frequencies up to 700 MHz. The differential input to
IN1,2 requires 0.1 µF ac coupling caps to be located
near the device and a 100  termination resistor to be
located between these caps and the transmission line
going back to the differential driver. See “AN408:
Termination Options for Any-Frequency, Any-Output
Clock Generators and Clock Buffers” for more
information on connecting input signals to IN1,2,3. This
application note can be downloaded from
www.silabs.com/timing.
2.3. Zero Delay Mode
A clock that is input to the Si5334 will have an
unspecified amount of delay from the input pins to the
output pins. The zero delay mode can be used to
reduce the delay through the Si5334 to typically less
than 100 ps. This is accomplished by feeding back the
CLK3 output to either IN4 or IN5,6. Using CLK3 allows
for an easy PCB route of this signal back to the input.
The R3 divider must be set to 1 when using feedback
from CLK3 to implement the zero delay mode. All output
clocks that are required to have zero delay must also
have their Rn divider set to 1. A single-ended signal up
to 200 MHz from CLK3 can be input to IN4. A single-
ended signal up to 350 MHz from CLK3 can be input to
IN5 using the technique shown in AN408. A differential
signal up to 710 MHz from CLK3a,b must be input to
IN5,IN6.
The IN4 input is electrically the same as IN3 described
above. The IN5,IN6 inputs are electrically the same as
the IN1,IN2 inputs described above. See AN408 for
additional information on signal connections for the zero
delay mode.
2.4. Breakthrough MultiSynth Technology
Next-generation timing IC architectures require a wide
range of frequencies which are often non-integer
related. Traditional clock architectures address this by
using multiple single PLL ICs, often at the expense of
BOM complexity and power. The Si5334 and Si5338
use patented MultiSynth technology to dramatically
simplify timing architectures by integrating the
frequency synthesis capability of 4 Phase-Locked
Loops (PLLs) in a single device, greatly minimizing size
and power requirements versus traditional solutions.
Based on a fractional-N PLL, the heart of the
architecture is a low phase noise, high frequency VCO.
The VCO supplies a high frequency output clock to the
MultiSynth block on each of the four independent output
paths. Each MultiSynth operates as a high speed
fractional divider with Silicon Labs' proprietary phase
error correction to divide down the VCO clock to the
required output frequency with very low jitter.
The first stage of the MultiSynth architecture is a
fractional-N divider which switches seamlessly between
the two closest integer divider values to produce the
exact output clock frequency with 0 ppm error. To
eliminate phase error generated by this process,
MultiSynth calculates the relative phase difference
between the clock produced by the fractional-N divider
and the desired output clock and dynamically adjusts
the phase to match the ideal clock waveform. This novel
approach makes it possible to generate any output
clock frequency without sacrificing jitter performance.
Rev. 1.2
15