SI5334 Datasheet, PDF (31/37 Pages) Silicon Laboratories – PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5334
Table 16. Si5334 Standard Frequency Plans (Continued)
Application
OPN
Si5334C-
B00161-GM
Input
Clock
CLKIN
Freq Format
74.1758
3.3 V
CMOS
CLK0
Freq Format
74.2500
3.3 V
CMOS
CLK1
Freq Format
74.2500
3.3 V
CMOS
CLK2
Freq Format
74.2500
3.3 V
CMOS
Si5334C-
B00162-GM
Clock
74.2500
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
Broadcast
Video
(Continued)
Si5334C-
B00163-GM
Si5334B-
B00164-GM
Clock 148.3516
Clock 148.3516
3.3 V
LVDS
3.3 V
LVDS
148.5000
270.0000
3.3 V
LVDS
3.3 V
LVDS
148.5000
270.0000
3.3 V
LVDS
3.3 V
LVDS
148.5000
270.0000
3.3 V
LVDS
3.3 V
LVDS
Si5334C-
B00165-GM
Clock 148.5000
3.3 V
LVDS
148.3516
3.3 V
LVDS
148.3516
3.3 V
LVDS
148.3516
3.3 V
LVDS
Si5334B-
B00166-GM
Clock 148.5000
3.3 V
LVDS
270.0000
3.3 V
LVDS
270.0000
3.3 V
LVDS
270.0000
PCIe*
Si5334M-
B00167-GM
Si5334M-
B00168-GM
Xtal
Clock
25.0000
25.0000
n/a 100.0000
3.3 V
CMOS
100.0000
3.3 V
HCSL
3.3 V
HCSL
100.0000
100.0000
3.3 V
HCSL
3.3 V
HCSL
100.0000
100.0000
Notes:
1. –0.5% downspread enabled on CLK0-CLK3
2. To request new frequency plans/device configurations, please contact your local Silicon Labs sales representative.
3.3 V
LVDS
3.3 V
HCSL
3.3 V
HCSL
CLK3
Freq
Format
74.2500 ^{3.3 V}
CMOS
74.1758 ^{3.3 V}
CMOS
148.5000
3.3 V
LVDS
3.3 V
270.0000 _LVDS
148.3516
3.3 V
LVDS
270.0000
100.0000
3.3 V
LVDS
3.3 V
HCSL
100.0000
3.3 V
HCSL
Rev. 1.2
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