SI5334 Datasheet, PDF (22/37 Pages) Silicon Laboratories – PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5334
Pin #
17
18
19
20
21
22
23
24
GND
PAD
Pin Name
CLK1B
CLK1A
OEB
VDDO0
CLK0B
CLK0A
RSVD_GND
VDD
GND
Table 15. Si5334 Pin Descriptions (Continued)
I/O
O
O
I
VDD
O
O
GND
VDD
GND
Signal Type
Multi
Multi
LVCMOS
Supply
Multi
Multi
GND
Supply
GND
Description
Output Clock B for Channel 1
May be a single-ended output or half of a differential
output with CLK1A being the other differential half.
If unused, this pin must be tied to VDD pin 24. If unused
leave this pin floating.
Output Clock A for Channel 1
May be a single-ended output or half of a differential
output with CLK1B being the other differential half. If
unused leave this pin floating.
Output Enable Low
When low, all the factory-programmed outputs are
enabled. When high all factory programmed outputs are
forced to a logic low.
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK0A,B.
A 0.1 µF capacitor must be located very close to this pin.
If CLK0 is not used, this pin must be tied to VDD (pin 7,
24).
Output Clock B for Channel 0
May be a single-ended output or half of a differential
output with CLK0A being the other differential half. If
unused leave this pin floating.
Output Clock A for Channel 0
May be a single-ended output or half of a differential
output with CLK0B being the other differential half. If
unused leave this pin floating.
Ground.
Must be connected to system ground.
Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A
0.1 µF bypass capacitor should be located very close to
this pin.
Ground Pad.
This is the large pad in the center of the package.
Device specifications cannot be guaranteed unless the
ground pad is properly connected to a ground plane on
the PCB. See section 6.0 for the PCB pad sizes and
ground via requirements.
22
Rev. 1.2