SI5334 Datasheet, PDF (16/37 Pages) Silicon Laboratories – PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5334
Based on this architecture, the output of each
MultiSynth can produce any frequency from 5 to Fvco/8
MHz. To support higher frequency operation, the
MultiSynth divider can be bypassed. In bypass mode
integer divide ratios of 4 and 6 are supported, which
allows for output frequencies of Fvco/4 and Fvco/6 MHz
which translates to 367–473.3 MHz and 550–710 MHz
respectively. Because each MultiSynth uses the same
VCO output there are output frequency limitations when
output frequencies greater than Fvco/8 are desired.
For example, if 375 MHz is needed at the output of
MultiSynth0, the VCO frequency would need to be
2.25 GHz. Now, all the other MultiSynths can produce
any frequency from 5 MHz up to a maximum frequency
of 2250/8 = 281.25 MHz. MultiSynth1,2,3 could also
produce Fvco/4 = 562.5 MHz or Fvco/6 = 375 MHz.
Only two unique frequencies above Fvco/8 can be
output: Fvco/6 and Fvco/4.
2.5. Output Driver
There are four clock output channels on the Si5334
(CLK0,CLK1,CLK2,CLK3) with two signal outputs per
channel. Each channel may be programmed to be a
differential driver or a dual single ended driver. If a
channel is factory-programmed to be single ended, then
the two outputs for that channel can be factory-
programmed to be in-phase or out-of-phase. Si5334
output drivers can be configured as single ended
CMOS, SSTL, HSTL or differential LVPECL, LVDS, and
HCSL formats.
The supply voltage requirement for each driver format is
selectable as shown in Table 14. All unused clock
output channels must have their respective VDD0x
supply voltage connected to pin 7 and 24 VDD.
MultiSynth
Fractional-N
f_VCO
Divider
Phase
Adjust
f_OUT
VDD0x
Supply
Voltage
1.5
1.8
2.5
3.3
Phase Error
Calculator
Divider Select
(DIV1, DIV2)
Figure 2. Silicon Labs’ MultiSynth Technology
Table 14. Output Driver Signal Format Selection
CMOS
SSTL
HSTL
LVPECL
LVDS
X
X
X
X
X
X
X
X
X
X
X
X
HCSL
X
X
X
16
Rev. 1.2