SI5334 Datasheet, PDF (7/37 Pages) Silicon Laboratories – PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5334
Table 4. Input and Output Clock Characteristics (Continued)
(V_DD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
0.16
—
350
Frequency⁴
f_OUT
LVPECL, LVDS
367
—
473.33
550
—
710
HCSL
0.16
—
250
LVPECL Output
Voltage
V_OC
V_SEPP
common mode
peak-to-peak single-
ended swing
—
0.55
V_DDO –
1.45 V
0.8
—
0.96
LVDS Output Voltage
(2.5/3.3 V)
V_OC
V_SEPP
common mode
peak-to-peak single-
ended swing
1.125
0.25
1.2
0.35
1.275
0.45
LVDS Output
Voltage (1.8 V)
V_OC
V_SEPP
common mode
peak-to-peak single-
ended swing
0.8
0.875
0.95
0.25
0.35
0.45
HCSL Output Voltage
V_OC
V_SEPP
common mode
peak-to-peak single-
ended swing
0.35
0.575
0.375
0.725
0.400
0.85
CML Output Voltage
V_OC
V_SEPP
Common Mode
Peak-to-Peak Single-
ended Swing
—
See
Note ⁵
—
0.67
0.860
1.07
Rise/Fall Time
t_R/t_F
Duty Cycle
DC
Output Clocks (Single-Ended)
20%–80%
—
—
450
45
—
55
Frequency
f_OUT
CMOS
SSTL, HSTL
0.16
—
200
0.16
—
350
CMOS 20%–80%
Rise/Fall Time
t_R/t_F
2 pF load
—
0.45
0.85
CMOS 20%–80%
Rise/Fall Time
t_R/t_F
15 pF load
—
—
2.0
Notes:
1. Use an external 100  resistor to provide load termination for a differential clock.
See "2.2. Crystal/Clock Input" on page 15.
2. For best jitter performance, keep the input slew rate on IN1/2, IN5/6 faster than 0.3 V/ns.
3. For best jitter performance, keep the input single ended slew rate on pins 3 or 4 faster than 1 V/ns.
4. Only two unique frequencies above Fvco/8 can be simultaneously output, Fvco/4 and Fvco/6.
5. CML output format requires ac-coupling of the differential outputs to a differential 100  load at the receiver.
6. Includes effect of internal series 22  resistor.
Units
MHz
MHz
MHz
MHz
V
V_PP
V
V_PP
V
V_PP
V
V_PP
V
V_PP
ps
%
MHz
MHz
ns
ns
Rev. 1.2
7