SI5334 Datasheet, PDF (21/37 Pages) Silicon Laboratories – PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Pin #
8
9
10
11
12
13
14
15
16
Si5334
Pin Name
LOSLOL
CLK3B
CLK3A
VDDO3
IN7
CLK2B
CLK2A
VDDO2
VDDO1
Table 15. Si5334 Pin Descriptions (Continued)
I/O
O
O
O
VDD
I
Signal Type
Open Drain
Multi
Multi
Supply
LVCMOS
Description
Loss of Signal or Loss of Lock Indicator.
0 = No LOS or LOL condition.
1 = A LOS or LOL condition has occurred.
For this pin a 1–5 k pull-up resistor to a voltage is
required. This voltage may be as high as 3.63 V
regardless of the voltage on pin 7.
Output Clock B for Channel 3
May be a single-ended output or half of a differential out-
put with CLK3A being the other differential half. If
unused leave this pin floating.
Output Clock A for Channel 3
May be a single-ended output or half of a differential
output with CLK3B being the other differential half. If
unused leave this pin floating.
Output Clock Supply Voltage
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK3A,B. A
0.1 µF capacitor must be located very close to this pin. If
CLK3 is not used, this pin must be tied to VDD (pin 7,
24).
SSPB*.
When low, Spread Spectrum is enabled on every output
clock that is programmed for Spread Spectrum. This
option is available on the Si5334K/L/M.
O
O
VDD
VDD
Multi
Multi
Supply
Supply
On an Si5334 that does not contain the spread spectrum
functionality, this pin should be connected to GND.
Output Clock B for Channel 2
May be a single-ended output or half of a differential
output with CLK2A being the other differential half. If
unused leave this pin floating.
Output Clock A for Channel 2
May be a single-ended output or half of a differential
output with CLK2B being the other differential half. If
unused leave this pin floating.
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK2A,B.
A 0.1 µF capacitor must be located very close to this pin.
If CLK2 is not used, this pin must be tied to VDD (pin 7,
24).
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK1A,B.
A 0.1 µF capacitor must be located very close to this pin.
If CLK1 is not used, this pin must be tied to VDD (pin 7,
24).
Rev. 1.2
21