SI5334 Datasheet, PDF (36/37 Pages) Silicon Laboratories – PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR

Si5334
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.15
 Updated tables for ac/dc specs to remove TBDs.
 Updated ordering OPN in Table 10 from 34C to
34M-00167/00168-GM.
 Updated SSC information for correct part number.
 Removed diagram in Section 3.
 Corrected Pin 12 description
 Removed low-power LVPECL mode.
 Updated pin descriptions to say 710 MHz.
 Added PCB layout notes on via requirements for
GND pad.
 Removed description of field programming as this is
not supported.
Revision 0.15 to Revision 0.16
 Changed cycle-cycle jitter spec from pk-pk to pk.
 Change refclk1 pin name to refclkse.
Revision 0.16 to Revision 1.0
 Updated Table 2, “DC Characteristics,” on page 4.
Updated dc characteristics for CMOS loads.
Added core supply current in buffer mode.
Added CML output buffer supply current in CML mode.
 Updated Table 3, “Performance Characteristics,” on
page 5.
PLL Lock Range test changed to PLL Tracking Range
and added typical specification.
Added Maximum Propragation Delay value.
 Updated Table 4, “Input and Output Clock
Characteristics,” on page 6.
Added CML Output specs.
Corrected VI to 3.73 V.
Corrected tR/tF (15 pF) to 2.0 ns.
Corrected LVPECL Output Voltage (typ) to
VDDO – 1.45.
 Updated Table 5, “Control Pins,” on page 9.
Updated V_IH to 3.73 V.
Corrected V_IL and V_OL.
 Expanded Tables 6–9 with recommended and
supported crystal load capacitance values.
 Updated Table 10, “Jitter Specifications¹,²,³,” on
page 11.
Updated typical specifications for total jitter for PCI
Express 1.1 Common clocked topology.
Updated typical specifications for RMS jitter for PCI
Express 2.1 Common clocked topology.
Removed RMS jitter specification for PCI Express 2.1
and 3.0 Data clocked topology.
 Updated Table 12, “Thermal Characteristics,” on
page 13.
 Updated Table 13, “Absolute Maximum Ratings¹,” on
page 13
Added MSL level information.
Added Peak Soldering Reflow Temperature.
 Corrected Table 15, “Si5334 Pin Descriptions,” on
page 19.
Changed “Supply” to “LVCMOS” for IN7 (pin 12).
 Updated and moved "5. Ordering Information and
Standard Frequency Plans" on page 25.
 Added "8. Top Marking" on page 34.
 Added "9. Device Errata" on page 35.
Revision 1.0 to Revision 1.1
 Removed down spread errata that has been
corrected in revision B.
 Updated ordering information to refer to Revision B
silicon.
 Updated top marking explanation in section 8.2.
 Updated “Device Pinout by Part Number” part
number references.
 Standard frequency plan OPNs in Table 16 updated
to reflect Rev B part numbers.
Revision 1.1 to Revision 1.2
 Added link to errata document.
36
Rev. 1.2