SI53305 Datasheet, PDF (8/36 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53305
Table 10. AC Characteristics (Continued)
(V_DD = V_DDOX = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Output Disable Time
T_DIS
F = 1 MHz
F = 100 MHz
—
2000
—
ns
—
30
—
ns
Output to Output Skew²
F = 725 MHz
—
T_SK
LVCMOS (12 mA drive to no load)
—
LVPECL
—
5
—
ns
50
120
ps
35
70
ps
Part to Part Skew³
Power Supply Noise
Rejection⁴
T_PS
PSRR
LVDS
Differential
10 kHz sinusoidal noise
100 kHz sinusoidal noise
—
35
70
ps
—
—
150
ps
—
–63
—
dBc
—
–62
—
dBc
500 kHz sinusoidal noise
—
–58
—
dBc
1 MHz sinusoidal noise
—
–55
—
dBc
Notes:
1. HCSL measurements were made with receiver termination. See Figure 9 on page 19.
2. Output to Output skew specified for outputs with an identical configuration.
3. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and
equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DDOX (3.3 V = 100 mV_PP) and noise spur
amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.
8
Rev. 1.0