SI53305 Datasheet, PDF (7/36 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53305
Table 10. AC Characteristics
(V_DD = V_DDOX = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 °C)
Parameter
Frequency
Symbol
Test Condition
Min
F LVPECL, low power LVPECL, LVDS, dc
CML, HCSL
(Glitchless switching to a min of 1
MHz)
LVCMOS
dc
(Glitchless switching to a min of 1
MHz)
Typ Max Unit
—
725 MHz
—
200 MHz
Duty Cycle
D_C
200 MHz, 20/80%T_R/T_F<10% of
40
50
60
%
Note: 50% input duty cycle.
period (LVCMOS)
(12 mA drive)
Minimum Input Clock
Slew Rate¹
20/80% T_R/T_F<10% of period
(Differential)
48
50
52
%
SR
Required to meet prop delay and 0.75
—
additive jitter specifications
(20–80%)
—
V/ns
Output Rise/Fall Time
T_R/T_F
LVDS, 20/80%
LVPECL, 20/80%
HCSL¹, 20/80%
—
—
325
ps
—
—
350
ps
—
—
280
ps
CML, 20/80%
—
—
350
ps
Low-Power LVPECL, 20/80%
—
—
325
ps
LVCMOS 200 MHz, 20/80%,
2 pF load
—
—
750
ps
Minimum Input Pulse
Width
Propagation Delay
T_W
500
—
—
ps
T_PLH, LVCMOS (12mA drive with no load) 1250 2000 2750
ps
T_PHL
LVPECL
600
800 1000
ps
LVDS
600
800 1000
ps
Output Enable Time
T_EN
F = 1 MHz
F = 100 MHz
—
2500
—
ns
—
30
—
ns
F = 725 MHz
—
5
—
ns
Notes:
1. HCSL measurements were made with receiver termination. See Figure 9 on page 19.
2. Output to Output skew specified for outputs with an identical configuration.
3. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and
equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DDOX (3.3 V = 100 mV_PP) and noise spur
amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.
Rev. 1.0
7