SI53305 Datasheet, PDF (26/36 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53305
3. Pin Description: 44-Pin QFN
OE2 ¹
SFOUT[0] 2
OE1 ³
Q2 ⁴
Q2 ⁵
GND ⁶
Q1 ⁷
Q1 ⁸
Q0 ⁹
Q0 ¹⁰
OE0 ¹¹
GND
PAD
33 _OE7
32 SFOUT[1]
31 _OE8
30 _Q7
29 _Q7
28 _NC
27 _Q8
26 _Q8
25 _Q9
24 _Q9
23 _OE9
Pin #
1
2
3
4
5
6
Name
OE2
SFOUT[0]
OE1
Q2
Q2
GND
Table 23. Pin Description
Description
Output enable-Output 2.
When OE2 = high, the Q2 is enabled.
When OE2 = low, Q2 is held low, and Q2 is held high for differential formats.
For LVCMOS, both Q2 and Q2 are held low when OE2 is set low.
OE2 contains an internal pull-up resistor.
Output signal format control pin [0].
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
Output enable-Output 1.
When OE1 = high, the Q1 is enabled.
When OE1 = low, Q1 is held low, and Q1 is held high for differential formats.
For LVCMOS, both Q1 and Q1 are held low when OE1 is set low.
OE1 contains an internal pull-up resistor.
Output clock 2 (complement).
Output clock 2.
Ground.
26
Rev. 1.0