SI53305 Datasheet, PDF(16/36 Page) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

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SI53305 Datasheet, PDF (16/36 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

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Si53305

2.5. Glitchless Clock Input Switching

The input clock mux features glitchless switching between two valid input clocks. Figure 7 illustrates that switching

between input clocks does not generate runt pulses or glitches at the output.

CLK1

CLK0

CLK_SEL

Note 1

Note 2

Note 3

Notes:

1. Qn continues with CLK0 for 2-3 falling edges of CLK0.

2. Qn is disabled low for 2-3 falling edges of CLK1 .

3. Qn starts on the first rising edge after 1 + 2.

Figure 7. Glitchless Input Clock Switch

Glitchless switching between 2 input clocks that are up to 10x different in frequency and between 1 MHz and 725

MHz is supported. When a switchover to a new clock is made, the output will disable low after two or three clock

cycles of the previously-selected input clock. The outputs will remain low for up to three clock cycles of the newly-

selected clock, after which the outputs will start from the newly-selected input. In the case a switchover to an

absent clock is made, the output will glitchlessly stop low and wait for edges of the newly selected clock. A

switchover from an absent clock to a live clock will also be glitchless. Note that the CLK_SEL input should not be

toggled faster than 1/250th the frequency of the slower input clock.

2.6. Synchronous Output Enable

This buffer features a synchronous output enable (disable) feature. Output enable is sampled and synchronized on

the falling edge of the input clock. This feature prevents runt pulses from being generated when the outputs are

enabled or disabled.

When OE is low, Q is held low and Q is held high for differential output formats. For LVCMOS output format

options, both Q and Q are held low when OE is set low. The device outputs are enabled when the output enable pin

is unconnected. See Table 10, âAC Characteristics,â on page 7 for output enable and output disable times.

2.7. Input Mux and Output Enable Logic

Two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects

the active clock input. The table below summarizes the input and output clock based on the input mux and output

enable pin settings.

Rev. 1.0

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