SI53305 Datasheet, PDF (27/36 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Pin #
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
Q1
Q1
Q0
Q0
OE0
V_DD
OE3
CLK0
CLK0
OE4
V_REF
OE5
CLK1
CLK1
Si53305
Table 23. Pin Description (Continued)
Output clock 1 (complement).
Description
Output clock 1.
Output clock 0 (complement).
Output clock 0.
Output enable-Output 0.
When OE0 = high, Q0 and Q0 outputs are enabled.
When OE0 = low, Q0 is held low, and Q0 is held high for differential formats.
For LVCMOS, both Q0 and Q0 are held low when OE0 is set low.
OE0 contains an internal pull-up resistor.
Core voltage supply.
Bypass with 1 µF capacitor placed as close to the V_DD pin as possible.
Output Enable 3.
When OE3 = high, Q3 and Q3 outputs are enabled.
When OE3 = low, Q3 is held low, and Q3 is held high for differential formats.
For LVCMOS, both Q3 and Q3 are held low when OE3 is set low.
OE3 contains an internal pull-up resistor.
Input clock 0.
Input clock 0 (complement).
When CLK0 is driven by a single-ended LVCMOS input, connect CLK0 to V_DD/2.
Output Enable 4.
When OE4 = high, Q4 and Q4 outputs are enabled.
When OE4 = low, Q4 is held low, and Q4 is held high for differential formats.
For LVCMOS, both Q4 and Q4 are held low when OE4 is set low.
OE4 contains an internal pull-up resistor.
Reference voltage for single-ended CMOS clocks.
V_REF is an output voltage and is equal to V_DD/2. See “2.3. Voltage Reference (VREF)”
for more details.
Output Enable 5.
When OE5 = high, Q5 and Q5 outputs are enabled.
When OE5 = low, Q5 is held low, and Q5 is held high for differential formats.
For LVCMOS, both Q5 and Q5 are held low when OE5 is set low.
OE5 contains an internal pull-up resistor.
Input clock 1.
Input clock 1 (complement).
When CLK1 is driven by a single-ended LVCMOS input, connect CLK1 to V_DD/2.
Rev. 1.0
27