SI53305 Datasheet, PDF (14/36 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53305
2.2. Input Bias Resistors
Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected.
The noninverting input is biased with a 18.75 k pulldown to GND and a 75 k pullup to V_DD. The inverting input is
biased with a 75 k pullup to V_DD.
V_DD
R_PU
R_PU
+
R_PD
CLK0 or
CLK1
–
R_PU = 75 kohm
R_PD = 18.75 kohm
Figure 5. Input Bias Resistors
2.3. Voltage Reference (V_REF)
The V_REF pin is used to bias the input receiver as shown in Figure 6 when a single-ended input clock (such as
LVCMOS) is used. Note that V_REF=V_DD/2 and should be compatible with the VCM rating of the single-ended input
clock driving the CLK0 or CLK1 inputs. To optimize jitter and duty cycle performance, use the circuit in Figure 3.
V_REF pin should be left floating when differential clocks are used.
V_{DDO = 3.3 V or 2.5 V}
50
Rs
CLKx
CLKx
Si53305
100 nF
V_REF
Figure 6. Using Voltage Reference with Single-Ended Input Clock
14
Rev. 1.0