SI53305 Datasheet, PDF (28/36 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53305
Pin #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Name
OE6
GND
OE9
Q9
Q9
Q8
Q8
NC
Q7
Q7
OE8
SFOUT[1]
OE7
V_DDOB
Q6
Q6
Q5
Q5
Table 23. Pin Description (Continued)
Description
Output Enable 6.
When OE6 = high, Q6 and Q6 outputs are enabled.
When OE6 = low, Q6 is held low, and Q6 is held high for differential formats.
For LVCMOS, both Q6 and Q6 are held low when OE6 is set low.
OE6 contains an internal pull-up resistor.
Ground.
Output Enable 9.
When OE9 = high, Q9 and Q9 outputs are enabled.
When OE9 = low, Q9 is held low, and Q9 is held high for differential formats.
For LVCMOS, both Q9 and Q9 are held low when OE9 is set low.
OE9 contains an internal pull-up resistor.
Output clock 9 (complement).
Output clock 9.
Output clock 8 (complement).
Output clock 8.
No connect.
Output clock 7 (complement).
Output clock 7.
Output Enable 8.
When OE8 = high, Q8 and Q8 outputs are enabled.
When OE8 = low, Q8 is held low, and Q8 is held high for differential formats.
For LVCMOS, both Q8 and Q8 are held low when OE8 is set low.
OE8 contains an internal pull-up resistor.
Output signal format control pin [1].
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
Output Enable 7.
When OE7 = high, Q7 and Q7 outputs are enabled.
When OE7 = low, Q7 is held low, and Q7 is held high for differential formats.
For LVCMOS, both Q7 and Q7 are held low when OE7 is set low.
OE7 contains an internal pull-up resistor.
Output Clock Voltage Supply—Bank B (Outputs: Q5 to Q9).
Bypass with a 1µF capacitor placed as close to the pin as possible.
Output clock 6 (complement).
Output clock 6.
Output clock 5 (complement).
Output clock 5.
28
Rev. 1.0