SI53305 Datasheet, PDF(1/36 Page) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

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SI53305 Datasheet, PDF (1/36 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53305

1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL

TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Features

ï® 10 differential or 20 LVCMOS outputsï® Low output-output skew: <70 ps

ï® Ultra-low additive jitter: 45 fs rms ï® Low propagation delay variation:

ï® Wide frequency range:

<400 ps

dc to 725 MHz

ï® Independent VDD and VDDO :

ï® Any-format input with pin selectable 1.8/2.5/3.3 V

output formats: LVPECL, Low Power ï® Excellent power supply noise

LVPECL, LVDS, CML, HCSL,

rejection (PSRR)

LVCMOS

ï® Selectable LVCMOS drive strength to

ï® 2:1 mux with hot-swappable inputs

tailor jitter and EMI performance

ï® Glitchless input clock switching

(1 MHz to 725 MHz)

ï® Individual output enable

ï® Synchronous output enable

ï® Small size: 44-QFN (7 mm x 7 mm)

ï® RoHS compliant, Pb-free

ï® Industrial temperature range:

â40 to +85 Â°C

Ordering Information:

See page 30.

Applications

ï® High-speed clock distribution

ï® Ethernet switch/router

ï® Optical Transport Network (OTN)

ï® SONET/SDH

ï® PCI Express Gen 1/2/3

ï® Storage

ï® Telecom

ï® Industrial

ï® Servers

ï® Backplane clock distribution

Description

The Si53305 is an ultra low jitter ten output differential buffer with pin-selectable

output clock signal format and individual OE. The Si53305 features a 2:1 mux with

glitchless switching, making it ideal for redundant clocking applications. The

Si53305 utilizes Silicon Laboratories' advanced CMOS technology to fanout

clocks from dc to 725 MHz with guaranteed low additive jitter, low skew, and low

propagation delay variability. The Si53305 features minimal cross-talk and

provides superior supply noise rejection, simplifying low jitter clock distribution in

noisy environments. Independent core and output bank supply pins provide

integrated level translation without the need for external circuitry.

Functional Block Diagram

Pin Assignments

Si53305

OE2 1

SFOUT[0] 2

OE1 3

Q2 4

Q2 5

GND 6

Q1 7

Q1 8

Q0 9

Q0 10

OE0 11

GND

PAD

33 OE7

32 SFOUT[1]

31 OE8

30 Q7

29 Q7

28 NC

27 Q8

26 Q8

25 Q9

24 Q9

23 OE9

Patents pending

VREF

Vref

Generator

Power

Supply

Filtering

CLK0

CLK1

CLK_SEL

Switching

Logic

VDDOA

OE[0:4]

Q0, Q1, Q2, Q3, Q4

SFOUT[1:0]

VDDOB

OE[5:9]

Q5, Q6, Q7, Q8, Q9

Rev. 1.0 9/15

Si53305

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