SI53305 Datasheet, PDF (29/36 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53305
Pin #
39
40
41
42
43
44
GND
Pad
Name
CLK_SEL
Q4
Q4
Q3
Q3
V_DDOA
GND
Table 23. Pin Description (Continued)
Description
MUX input select pin (LVCMOS).
Clock inputs are switched without the introduction of glitches.
When CLK_SEL is high, CLK1 is selected.
When CLK_SEL is low, CLK0 is selected.
CLK_SEL contains an internal pull-down resistor.
Output clock 4 (complement).
Output clock 4.
Output clock 3 (complement).
Output clock 3.
Output Voltage Supply—Bank A (Outputs: Q0 to Q4).
Bypass with a 1µF capacitor placed as close to the pin as possible.
Ground Pad
Power supply ground and thermal relief.
Rev. 1.0
29