SI53305 Datasheet, PDF (25/36 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE

Si53305
2.12. Input Mux Noise Isolation
The buffer’s input clock mux is designed to minimize crosstalk between the CLK0 and CLK1. This improves phase
jitter performance when clocks are present at both the CLK0 and CLK1 inputs. Figure 16 below is a measurement
the input mux’s noise isolation.
LVPECL output@156.25MHz;
Selected clk is active
Unselected clk is static
LVPECL output@156.25MHz;
Selected clk is static
Unselected clk is active
Mux Isolation = 61dB
Figure 16. Input Mux Noise Isolation
2.13. Power Supply Noise Rejection
The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low
jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and
SoCs and may reduce board-level filtering requirements. For more information, see “AN491: Power Supply
Rejection for Low Jitter Clocks”.
Rev. 1.0
25