SI53301 Datasheet, PDF (8/34 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53301
Table 10. AC Characteristics (Continued)
(V_DD = V_DDOX = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 °C)
Parameter
Power Supply Noise
Rejection⁵
Symbol
PSRR
Test Condition
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
Min Typ Max Unit
—
–65
—
dBc
—
–63
—
dBc
—
–60
—
dBc
1 MHz sinusoidal noise
—
–55
—
dBc
Notes:
1. When using the on-chip clock divider, a minimum input clock slew rate of 30 mV/ns is required.
2. HCSL measurements were made with receiver termination. See Figure 9 on page 19.
3. Output to Output skew specified for outputs with an identical configuration.
4. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and and
equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
5. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DDOX (3.3 V = 100 mV_PP) and noise spur
amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.
8
Rev. 1.1