SI53301 Datasheet, PDF (12/34 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53301
2. Functional Description
The Si53301 is a low jitter, low skew 1:6 differential buffer with an integrated 2:1 input mux. The device has a
universal input that accepts most common differential or LVCMOS input signals. A clock select pin is used to select
the active input clock. The selected clock input is routed to two independent banks of three differential clock
outputs (Bank A and Bank B). Each output bank features control pins to select signal format, output enable, output
divider setting and LVCMOS drive strength.
2.1. Universal, Any-Format Input
The Si53301 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including
LVPECL, low-power LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 15 and 16 summarize the various ac- and
dc-coupling options supported by the device. For the best high-speed performance, the use of differential formats
is recommended. For both single-ended and differential input clocks, the fastest possible slew rate is
recommended as low slew rates can increased the noise floor and degrade jitter performance. Though not
required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended
formats. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more
information.
Table 15. LVPECL, LVCMOS, and LVDS Input Clock Options
1.8 V
2.5/3.3 V
LVPECL
AC-Couple
DC-Couple
N/A
N/A
Yes
Yes
LVCMOS
AC-Couple
DC-Couple
No
No
No
Yes
LVDS
AC-Couple
DC-Couple
Yes
No
Yes
Yes
1.8 V
2.5/3.3 V
Table 16. HCSL and CML Input Clock Options
AC-Couple
No
Yes (3.3 V)
HCSL
DC-Couple
No
Yes (3.3 V)
AC-Couple
Yes
Yes
CML
DC-Couple
No
No
0.1 µF
CLKx
Si533xx
100 
/CLKx
0.1 µF
Figure 2. Differential HCSL, LVPECL, Low-Power LVPECL, LVDS, CML AC-Coupled Input
Termination
VDDO = 3.3 V or 2.5 V
CMOS
Driver
Rs
VDD
1 k
VDD
Si533xx
50
CLKx
/CLKx
VTERM = VDD/2
1 k
VREF
Figure 3. LVCMOS DC-Coupled Input Termination
12
Rev. 1.1