SI53301 Datasheet, PDF (17/34 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53301
2.8. Input Mux and Output Enable Logic
The Si53301 provides two clock inputs for applications that need to select between one of two clock sources. The
CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the
input mux and output enable pin settings.
Table 19. Input Mux and Output Enable Logic
CLK_SEL
CLK0
CLK1
OE¹
Q²
L
L
X
H
L
L
H
X
H
H
H
X
L
H
L
H
X
H
H
H
X
X
X
L
L³
Notes:
1. Output enable active high
2. On the next negative transition of CLK0 or CLK1.
3. Single-end: Q = low, Q = low
Differential: Q = low, Q = high
2.9. Loss of Signal (LOS) Indicator
The LOS0 and LOS1 indicators are used to check for the presence of input clocks CLK0 and CLK1. The LOS0 and
LOS1 pins are checked prior to selecting that clock input or are polled to check for the presence of the currently
selected input clock. In the event that an input clock is not present, the associated LOSx pin will assume a logic
high (LOSx = 1) state. When a clock is present at the associated input clock pin, the LOSx pin will assume a logic
low (LOSx = 0) state.
2.10. Power Supply (V_DD and V_DDOX)
The device includes separate core (V_DD) and output driver supplies (V_DDOX). This feature allows the core to
operate at a lower voltage than V_DDO, reducing current consumption in mixed supply applications. The core V_DD
supports 3.3 V, 2.5 V, or 1.8 V. Each output bank has its own V_DDOX supply, supporting 3.3 V, 2.5 V, or 1.8 V.
Rev. 1.1
17